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853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 1 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer g eneral d escription the ics853310 is a low skew, high perfor- mance 1-to-8 differential-to-3.3v lvp ecl/ecl fanout buffer and a member of the hiperclocks? family of high performance clock solutions from ics. the pclkx, npclkx pairs can accept lvpecl, lvds, cml and sstl differential input levels. the ics853310 is characterized to operate from a 3.3v power supply. guaranteed output and part-to-part skew characteristics make the ics853310 ideal for those clock distribution applications demanding well defined per- formance and repeatability. f eatures ? eight differential 3.3v lvpecl / ecl outputs ? two selectable differential lvpecl input pairs ? pclkx, npclkx pairs can accept the following differential input levels: lvpecl, lvds, cml, sstl ? output frequency: >2ghz (typical) ? translates any single ended input signal to 3.3v lvpecl levels with resistor bias on npclkx input ? output skew: 50ps (maximum) ? part-to-part skew: 200ps (maximum) ? propagation delay: 900ps (maximum) ? lvpecl mode operating voltage supply range: v cc = 3v to 3.8v, v ee = 0v ? ecl mode operating voltage supply range: v cc = 0v, v ee = -3v to -3.8v ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs-compliant packages b lock d iagram p in a ssignment hiperclocks? ic s 28-lead plcc 11.6mm x 11.4mm x 4.1mm package body v package top view q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 q6 nq6 q7 nq7 pclk0 npclk0 0 1 pclk1 npclk1 clk_sel ics853310 25 24 23 22 21 20 19 5 6 7 8 9 10 11 26 27 28 1 2 3 4 18 17 16 15 14 13 12 v ee clk_sel pclk0 v cc npclk0 v bb pclk1 npclk1 nc nq7 v cco q7 nq6 q6 nq2 q2 nq1 v cco q1 nq0 q0 q3 nq3 q4 v cco nq4 q5 nq5 v bb
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 2 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 1v c c r e w o p. n i p y l p p u s e r o c 20 k l c p nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i c c . 2 / 3v b b t u p t u o. e g a t l o v s a i b 41 k l c pt u p n in w o d l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i - n o n 51 k l c p nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i c c . 2 / 6c nd e s u n u. t c e n n o c o n 9 , 77 q , 7 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 2 2 , 5 1 , 8v o c c r e w o p. s n i p y l p p u s t u p t u o 1 1 , 0 16 q , 6 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 3 1 , 2 15 q , 5 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 6 1 , 4 14 q , 4 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8 1 , 7 13 q , 3 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 0 2 , 9 12 q , 2 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 3 2 , 1 21 q , 1 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 2 , 4 20 q , 0 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 6 2v e e r e w o p. n i p y l p p u s e v i t a g e n 7 2l e s _ k l ct u p n in w o d l l u p n e h w . s t u p n i 1 k l c p n , 1 k l c p s t c e l e s , h g i h n e h w . t u p n i t c e l e s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p n i 0 k l c p n , 0 k l c p s t c e l e s , w o l 8 20 k l c pt u p n in w o d l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i - n o n
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 3 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer t able 2a. lvpecl p ower s upply dc c haracteristics , v cc = 3v to 3.8v; v ee = 0v table 2b. lvpecl dc characteristics, v cc = 3.3v; v ee = 0v l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 0 . 33 . 38 . 3v v o c c e g a t l o v y l p p u s t u p t u o 0 . 33 . 38 . 3v i e e t n e r r u c y l p p u s r e w o p 0 7a m a bsolute m aximum r atings supply voltage, v cc 4.6v (lvpecl mode, v ee = 0) negative supply voltage, v ee -4.6v (lvecl mode, v cc = 0) inputs, v i (lvpecl mode) -0.5v to v cc + 0.5 v inputs, v i (lvecl mode) 0.5v to v ee - 0.5v outputs, i o continuous current 50ma surge current 100ma v bb sink/source, i bb 0.5ma operating temperature range , ta -40c to +85c storage temperature, t stg -65c to 150c wave solder, t sol 265c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifi- cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect product reliability. l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 - t i n u s n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 7 1 . 25 7 2 . 28 3 . 25 2 2 . 25 9 2 . 27 3 . 25 9 2 . 22 2 . 25 6 3 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 0 4 . 15 4 5 . 18 6 . 15 2 4 . 12 5 . 15 1 6 . 14 4 . 15 3 5 . 13 6 . 1v v h i e g a t l o v h g i h t u p n i d e d n e - e l g n i s ( ) 5 7 0 . 26 3 . 25 7 0 . 26 3 . 25 7 0 . 2v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 3 4 . 15 6 7 . 13 4 . 15 6 7 . 13 4 . 15 6 7 . 1v v b b 2 e t o n ; e c n e r e f e r e g a t l o v t u p t u o 6 8 . 18 9 . 16 8 . 18 9 . 16 8 . 18 9 . 1v m v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 0 50 0 0 10 0 50 0 0 10 0 50 0 0 1v m v r m c e g a t l o v h g i h t u p n i 3 e t o n ; e g n a r e d o m n o m m o c 8 . 19 . 28 . 19 . 28 . 19 . 2v i h i h g i h t u p n i t n e r r u c 1 k l c p , 0 k l c p 1 k l c p n , 0 k l c p n l e s _ k l c 0 5 10 5 10 5 1a i l i w o l t u p n i t n e r r u c , 1 k l c p , 0 k l c p 1 k l c p n , 0 k l c p n l e s _ k l c 0 5 1 -0 5 1 -0 5 1 -a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i : 1 e t o n c c v . e e . v 3 . 0 y r a v n a c . " t i u c r i c t s e t c a d a o l t u p t u o " , n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p o t r e f e r e s a e l p 0 5 h t i w d e t a n i m r e t s t u p t u o : 2 e t o n v o t o c c . v 2 - v : 3 e t o n r m c v h t i w 1 : 1 s e i r a v n i m e e v h t i w 1 : 1 s e i r a v x a m , c c v . r m c e h t h c i h w n i h t i w e g n a r e h t s a d e n i f e d s iv h i y a m l e v e l v e h t . n o i t a c i f i c e p s y a l e d n o i t a g a p o r p e h t g n i t e e m l l i t s e c i v e d e h t h t i w , y r a v l i k a e p - o t - k a e p e h t t a h t h c u s e b t s u m l e v e l o t l a u q e r o n a h t r e t a e r g d n a v 1 n a h t s s e l s i e g a t l o vv p p . ) n i m (
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 4 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer table 2d. ecl dc characteristics, v cc = 0v; v ee = -3.3v 0.3v t able 3. ac c haracteristics , v cc = 3.3v; v ee = 0v or v cc = 0v; v ee = -3.3v l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m f x a m y c n e u q e r f t u p t u o2 >2 >2 >z h g t d p 1 e t o n ; y a l e d n o i t a g a p o r p0 0 70 0 90 5 70 5 95 7 75 7 9s p t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o5 70 50 5s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p0 5 20 0 20 0 2s p t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 10 0 40 0 10 0 40 0 10 0 4s p v e e . v 3 . 0 y r e v n a c ? t a d e r u s a e m s r e t e m a r a p l l a . e s i w r e h t o d e t o n s s e l n u z h g 2 . 1 . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n . s t n i o p s s o r c l a i t n e r e f f i d e h t t a d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n t able 2c. lvecl p ower s upply dc c haracteristics , v cc = 0v; v ee = -3.3v 0.3v l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v e e e g a t l o v y l p p u s 0 . 3 -3 . 3 -8 . 3 -v i e e t n e r r u c y l p p u s r e w o p 0 7a m l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o e g a t l o v h g i h t u p t u o 5 2 1 . 1 -5 2 0 . 1 -2 9 . 0 -5 7 0 . 1 -5 0 0 . 1 -3 9 . 0 -5 0 0 . 1 -8 0 . 1 -5 3 9 . 0 - v v l o e g a t l o v w o l t u p t u o 5 9 8 . 1 -5 5 7 . 1 -2 6 . 1 -5 7 8 . 1 -8 7 . 1 -5 8 6 . 1 -6 8 . 1 -5 6 7 . 1 -7 6 . 1 - v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 2 2 . 1 -4 9 . 0 -5 2 2 . 1 -4 9 . 0 -5 2 2 . 1 - v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 7 8 . 1 -5 3 5 . 1 -7 8 . 1 -5 3 5 . 1 -7 8 . 1 -5 3 5 . 1 - v v b b ; e c n e r e f e r e g a t l o v t u p t u o 1 e t o n 4 4 . 1 -2 3 . 1 -4 4 . 1 -2 3 . 1 -4 4 . 1 -2 3 . 1 - v m v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 0 50 0 0 10 0 50 0 0 10 0 50 0 0 1 v m v r m c e g a t l o v h g i h t u p n i 2 e t o n ; e g n a r e d o m n o m m o c 5 . 14 . 0 -5 . 14 . 0 -5 . 14 . 0 - v i h i h g i h t u p n i t n e r r u c , 1 k l c p , 0 k l c p 1 k l c p n , 0 k l c p n l e s _ k l c 0 5 10 5 10 5 1 a l i i w o l t u p n i t n e r r u c , 1 k l c p , 0 k l c p 1 k l c p n , 0 k l c p n l e s _ k l c 0 5 1 -0 5 1 -0 5 1 - a 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 - v : 2 e t o n r m c v h t i w 1 : 1 s e i r a v n i m e e v h t i w 1 : 1 s e i r a v x a m , c c v . r m c e h t h c i h w n i h t i w e g n a r e h t s a d e n i f e d s iv h i y a m l e v e l v e h t . n o i t a c i f i c e p s y a l e d n o i t a g a p o r p e h t g n i t e e m l l i t s e c i v e d e h t h t i w , y r a v l i k a e p - o t - k a e p e h t t a h t h c u s e b t s u m l e v e l o t l a u q e r o n a h t r e t a e r g d n a v 1 n a h t s s e l s i e g a t l o vv p p . ) n i m (
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 5 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer p arameter m easurement i nformation o utput s kew d ifferential i nput l evel o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.3v 0.3v p art - to -p art s kew t sk(o) qy qx v cmr cross points v pp v ee pclk0, pclk1 npclk0, npclk1 v cc nqy nqx clock outputs 20% 80% 80% 20% t r t f v sw i n g t pd pclk0, pclk1 npclk0, npclk1 p ropagation d elay nqx qx nqy qy pa r t 1 pa r t 2 t sk(pp) o utput r ise /f all t ime nq0:nq7 q0:q7 v ee v cc
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 6 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer a pplication i nformation f igure 1a. s ingle e nded lvcmos s ignal d riving d ifferential i nput figure 1a shows an example of the differential input that can be wired to accept single ended lvcmos levels. the reference voltage level v bb generated from the device is w iring the d ifferential i nput to a ccept s ingle e nded lvcmos l evels connected to the negative input. the c1 capacitor should be located as close as possible to the input pin. f igure 1b. s ingle e nded lvpecl s ignal d riving d ifferential i nput figure 1b shows an example of the differential input that can be wired to accept single ended lvpecl levels. the reference voltage level v bb generated from the device is connected to the negative input. w iring the d ifferential i nput to a ccept s ingle e nded lvpecl l evels vcc r2 1k v_ref c1 0.1u r1 1k single ended clock input pclk npclk vcc(or vdd) clk_in pclk npclk vbb
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 7 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer lvpecl c lock i nput i nterface the pclk /npclk accepts lv pecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2f show inter- face examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input inter- faces suggested here are examples only. if the driver is from another vendor, use their termination recommenda- tion. please consult with the vendor of the driver compo- nent to confirm the driver termination requirements. f igure 2a. h i p er c lock s pclk/npclk i nput d riven by an o pen c ollector cml d river f igure 2b. h i p er c lock s pclk/npclk i nput d riven by a b uilt -i n p ullup cml d river f igure 2c. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river f igure 2f. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvds d river pclk/npclk 2.5v zo = 60 ohm sstl hiperclocks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v f igure 2e. h i p er c lock s pclk/npclk i nput d riven by an sstl d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm f igure 2d. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river with ac c ouple 3.3v 3.3v cml built-in pullup r1 100 pclk npclk hiperclocks pclk/npclk zo = 50 ohm zo = 50 ohm r2 50 zo = 50 ohm c1 r1 50 c2 pclk/npclk r5 100 - 200 zo = 50 ohm r6 100 - 200 pclk npclk vbb 3.3v lvpecl 3.3v 3.3v lvds 3.3v zo = 50 ohm 3.3v pclk npclk vbb r2 1k c2 r1 1k r5 100 c1 pclk/npclk zo = 50 ohm
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 8 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 the clock layout topology shown below is a typical termi- nation for lvpecl outputs. the two different layouts men- tioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched imped- ance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination i nputs : pclk/npclk i nput : for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k resistor can be tied from pclk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. r ecommendations for u nused i nput and o utput p ins
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 9 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer zo = 50 zo = 50 ohm + - c7 (option) 0.1u c5 (option) 0.1u zo = 50 (u1-1) c6 (option) 0.1u r8 50 r3 50 u1 ics853310 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 27 26 25 24 23 22 21 28 vcc npclk0 vbb pclk1 npclk1 nc nq7 vcco q7 nq6 q6 nq5 q5 nq4 vcco q4 nq3 q3 nq2 q2 clk_sel vee q0 nq0 q1 vcco nq1 pclk0 c3 0.1uf 3.3v vcc (u1-22) (u1-15) vcc=3.3v r10 50 + - zo = 50 ohm lvpecl driv er r1 50 r13 50 vcc zo = 50 c1 0.1uf r7 50 zo = 50 r3 1k r9 50 c4 0.1uf c2 0.1uf vcc (u1-8) r2 50 r11 50 s chematic e xample figure 4a shows a schematic example of the ics853310. in this example, the pclk0/npclk0 input is selected. the decoupling capacitors should be physically located near the power pin. for ics853310, the unused outputs can be left floating. f igure 4a. ics853310 lvpecl c lock o utput b uffer s chematic e xample
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 10 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer p ower , g round and b ypass c apacitor this section provides a layout guide related to power, ground and placement of bypass capacitors for a high-speed digital ic. this layout guide is a general recommendation. the actual board design will depend on the component types being used, the board density and cost constraints. this description assumes that the board has clean power and ground planes. the goal is to mini- mize the esr between the clean power/ground plane and the ic power/ground pin. a low esr bypass capacitor should be used on each power pin. the value of bypass capacitors ranges from 0.01uf to 0.1uf. the bypass capacitors should be located as close to the power gnd ic power pin gnd pin via gnd pad c power pad f igure 4b. r ecommended l ayout of b ypass c apacitor p lacement pin as possible. it is preferable to locate the bypass capacitor on the same side as the ic. figure 4b shows suggested capacitor placement. placing the bypass capacitor on the same side as the ic allows the capacitor to have direct contact with the ic power pin. this can avoid any vias between the bypass capaci- tor and the ic power pins. the vias should be placed at the power/ground pads. there should be a minimum of one via per pin. increasing the number of vias from the power/ground pads to power/ground planes can im- prove the conductivity.
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 11 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 37. 8c/w 31.1c/w 28.3c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics853310. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics853310 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.8v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.8v * 70ma = 266mw ? power (outputs) max = 30.94mw/loaded output pair if all outputs are loaded, the total power is 8 * 30.94mw = 247.5mw total power _max (3.8v, with all outputs switching) = 266mw + 247.5mw = 513.5mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature i n order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1c/w per table 4 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.514w * 31.1c/w = 101c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 4. t hermal r esistance ja for 28- pin plcc, f orced c onvection
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 12 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer 3. calculations and equations. lvpecl output driver circuit and termination are shown in figure 5. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.935v (v cco_max - v oh_max ) = 0.935v ? for logic low, v out = v ol_max = v cco_max ? 1.67v (v cco_max - v ol_max ) = 1.67v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco _max - v oh_max )) /r l ] * (v cco _max - v oh_max ) = [(2v - 0.935v)/50 ] * 0.935v = 19.92mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco _max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.67v)/50 ] * 1.67v = 11.02mw total power dissipation per output pair = pd_h + pd_l = 30.94mw figure 5. lvpecl driver circuit and termination q1 v out v cco rl 50 v cco - 2v
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 13 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer r eliability i nformation t ransistor c ount the transistor count for ics853310 is: 462 pin compatible with mc100lve310 t able 5. ja vs . a ir f low t able for 28 l ead plcc ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 37.8c/w 31.1c/w 28.3c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 14 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer p ackage o utline - v s uffix for 28 l ead plcc n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y sm u m i n i mm u m i x a m n 8 2 a 9 1 . 47 5 . 4 1 a 9 2 . 25 0 . 3 2 a 7 5 . 11 1 . 2 b 3 3 . 03 5 . 0 c 9 1 . 02 3 . 0 d 2 3 . 2 17 5 . 2 1 1 d 3 4 . 1 18 5 . 1 1 2 d 5 8 . 46 5 . 5 e 2 3 . 2 17 5 . 2 1 1 e 3 4 . 1 18 5 . 1 1 2 e 5 8 . 46 5 . 5 t able 6. p ackage d imensions reference document: jedec publication 95, ms-018
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 15 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer t able 7. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extr aordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademark, hiperclocks is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t v a 0 1 3 3 5 8 s c iv a 0 1 3 3 5 8 s c ic c l p d a e l 8 2e b u tc 5 8 o t c 0 4 - t v a 0 1 3 3 5 8 s c iv a 0 1 3 3 5 8 s c il e e r d n a e p a t n o c c l p d a e l 8 2l e e r & e p a t 0 0 5c 5 8 o t c 0 4 - f l v a 0 1 3 3 5 8 s c il v a 0 1 3 3 5 8 s c ic c l p " e e r f - d a e l " d a e l 8 2e b u tc 5 8 o t c 0 4 - t f l v a 0 1 3 3 5 8 s c il v a 0 1 3 3 5 8 s c ic c l p " e e r f - d a e l " d a e l 8 2l e e r & e p a t 0 0 5c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
853310av www.icst.com/products/hiperclocks.html rev. a november 22, 2005 16 integrated circuit systems, inc. ics853310 l ow s kew , 1- to -8 d ifferential - to -3.3v lvpecl/ecl f anout b uffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a 7 t 1 8 5 1 . g n i c a p s r e b m u n n i p t n e m n g i s s a n i p d e t c e r r o c . t e l l u b e e r f - d a e l d d a d e d d a . s n i p t u p t u o d n a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r . r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 4 1 / 9 a7 t5 1. g n i k r a m e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 2 2 / 1 1

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